Atomera Technology Supported by Synopsys Sentaurus in Latest Release
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Industry leading Sentaurus TCAD software will assist design engineers in modeling Atomera–s semiconductor performance enhancement technology
Industry leading Sentaurus TCAD software will assist design engineers in modeling Atomera–s semiconductor performance enhancement technology
Six new products using three different silicon providers have achieved certification at the event in China: ARRIS, CIG, Comtrend, NetBit, Zinwell and ZTE
SAN JOSE, CA — (Marketwired) — 09/10/15 — eSilicon Corporation, Northwest Logic and SK Hynix today announced they have created a fully working HBM hardware demonstration. This demonstration uses an advanced FPGA containing Northwest Logic–s HBM Controller Core and FPGA-based HBM PHY and SK Hynix HBM devices. eSilicon packaged the FPGA and HBM devices on an organic interposer. This demonstration is further indication that HBM is ready to be used by the market to implement a wide variety of h
While Materials Like SiC and GaN Are Making Gains, Silicon Will Maintain an 87% Market Share in 2024 Through Advances in Circuits, Controls, and Packaging, Says Lux Research
SAN JOSE, CA — (Marketwired) — 04/29/15 –Javier DeLaCruz, eSilicon–s senior director of product strategyHoliday Inn Conference Center
242 Adams
Boxborough, Massachusetts 01719May 5, 2015
10:40 AMVarious market dynamics are influencing the adoption of 2.5D integration. Recent developments have enabled 2.5D to provide feature enhancements, but if applied well may also provide significant cost benefits over what can be otherwise executed.As a senior director of product strategy at eSilicon Cor
SAN JOSE, CA — (Marketwired) — 04/16/15 –DoubleTree by Hilton Hotel San Jose
2050 Gateway Place
San Jose, California 95110April 21, 2015Daniel Nenni, SemiWiki.com CEO & FounderJack Harding, eSilicon, president & CEOWally Rhines, Mentor Graphics, CEO & COBGiorgio Cesana, STMicroelectronics, director of technologyLluis Paris, TSMC, deputy director of worldwide IP allianceThe system on chip (SoC) business seriously challenged the semiconductor foundries at 28nm with increased integr
Customizing Memory IP for IoT Applications
eSilicon–s Lisa Minwell Will Discuss Technologies and Techniques for Optimizing 2.5D Designs for Power and Cost Effectiveness at MEPTEC
PVD Tool Optimization Results in the Industry–s Highest TSV Step Coverage for Interposers and 3D ICs
New One-Click Access to Automated Online MPW and GDSII Quoting Portals