Sidense Presenting at TSMC and ChipEstimate.com Booths at the Design Automation Conference in San Francisco

Sidense Presenting at TSMC and ChipEstimate.com Booths at the Design Automation Conference in San Francisco

OTTAWA, ON and SAN JOSE, CA — (Marketwired) — 05/28/15 –Sidense will be presenting in the ChipEstimate.com booth (#2433) and in the TSMC OIP Theatre (#1933).The ChipEstimate.com presentation will be on and will take place at the following times:Tuesday, June 9 at 2:30PM
Wednesday, June 10 at 1:30PMSidense CTO Wlodek Kurjanowicz will present in the OIP Theatre at the following times:Monday, June 8 at 11:30AM
Tuesday, June 9 at 3:15PM
Wednesday, June 10 at 2:00PMMoscone Center
800 Howard St.

MEDIA ALERT: Sidense White Paper Discusses the Use of 1T-OTP Memory for Optimizing Sensor Performance

MEDIA ALERT: Sidense White Paper Discusses the Use of 1T-OTP Memory for Optimizing Sensor Performance

OTTAWA, ON and SANTA CLARA, CA — (Marketwired) — 12/03/13 –Sidense has released a white paper, "Optimizing Sensor Performance with 1T-OTP Trimming," discussing the advantages of using antifuse-based one-transistor, one-time programmable (1T-OTP) memory to trim sensors.Variations in component and circuit characteristics, along with chip processing and packaging operations, result in deviations of analog circuits and sensors from their target specifications. To optimize the performanc

MEDIA ALERT: Sidense Exhibiting at the SMIC Technology Symposium in Shanghai, China

MEDIA ALERT: Sidense Exhibiting at the SMIC Technology Symposium in Shanghai, China

OTTAWA, ON and SANTA CLARA, CA — (Marketwired) — 08/29/13 –Sidense will be exhibiting at the Semiconductor Manufacturing International Corporation (SMIC) Technology Symposium and discussing its low-cost, secure and reliable 1T-OTP non-volatile memory (NVM) IP, available from 180nm to 20nm including HV and BCD process nodes.Shanghai Dongjiao State Guest Hotel
No.1800 Jin Ke Road
Pudong New Area, Shanghai ChinaSeptember 4, 2013
9AM to 4:30PMFor more information or to schedule a meeting with Sid

MEDIA ALERT: Sidense Exhibiting at TSMC Technology Symposiums

MEDIA ALERT: Sidense Exhibiting at TSMC Technology Symposiums

OTTAWA and SANTA CLARA, CA — (Marketwired) — 04/02/13 –Sidense will be exhibiting at the U.S. TMSC Technology Symposiums and discussing its low-cost, secure and reliable 1T-OTP non-volatile memory (NVM) IP, available from 180nm to 20nm including HV and BCD process nodes.San Jose McEnery Convention Center
150 West San Carlos Street
San Jose, CA 95113
Booth #503The Westin Austin at the Domain
11301 Domain Drive
Austin, TX 78758The Westin-Waltham Boston
70 3rd Ave
Waltham, MA 02451San Jose on T