eSilicon CEO Jack Harding to Participate in Global Semiconductor Alliance CEO Panel “What–s next”

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eSilicon CEO Jack Harding to Participate in Global Semiconductor Alliance CEO Panel “What–s next”

SAN JOSE, CA — (Marketwired) — 04/14/16 — Led by Dr. Aart de Geus, chairman and co-CEO of Synopsys, a panel of CEOs will answer the question, "What–s next?" at the GSA European Executive Forum on April 19, 2016 in Munich, Germany.Simply put, there are enormous changes going on simultaneously in the semi industry: massive and difficult technology evolutions, horizontal and vertical reconfiguration of the industry via consolidation, maturing and price competition in the mobility mar

indie Semiconductor Announces Certification of World–s Smallest USB-C E-Marker Chip

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indie Semiconductor Announces Certification of World–s Smallest USB-C E-Marker Chip

ALISO VIEJO, CA — (Marketwired) — 03/16/16 — indie Semiconductor announced today that the USB Implementers Forum (USB-IF) Compliance Program has certified the new indie iND80001 Lodestar chip as USB-C and USB PD 2.0 compliant. The chip utilizes E-Marker technology to facilitate USB power delivery. At less than 1mm on a side, it is the smallest device available.is designed to fit inside cables and forms part of the power delivery mechanism for the new USB-C cables that are set to take over th

eSilicon, Northwest Logic and SK Hynix Create High-Bandwidth Memory (HBM) Hardware Demonstration

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eSilicon, Northwest Logic and SK Hynix Create High-Bandwidth Memory (HBM) Hardware Demonstration

SAN JOSE, CA — (Marketwired) — 09/10/15 — eSilicon Corporation, Northwest Logic and SK Hynix today announced they have created a fully working HBM hardware demonstration. This demonstration uses an advanced FPGA containing Northwest Logic–s HBM Controller Core and FPGA-based HBM PHY and SK Hynix HBM devices. eSilicon packaged the FPGA and HBM devices on an organic interposer. This demonstration is further indication that HBM is ready to be used by the market to implement a wide variety of h

eSilicon–s Javier DeLaCruz to Present: Cost Structure Advantages of 2.5D Integration

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eSilicon–s Javier DeLaCruz to Present: Cost Structure Advantages of 2.5D Integration

SAN JOSE, CA — (Marketwired) — 04/29/15 –Javier DeLaCruz, eSilicon–s senior director of product strategyHoliday Inn Conference Center
242 Adams
Boxborough, Massachusetts 01719May 5, 2015
10:40 AMVarious market dynamics are influencing the adoption of 2.5D integration. Recent developments have enabled 2.5D to provide feature enhancements, but if applied well may also provide significant cost benefits over what can be otherwise executed.As a senior director of product strategy at eSilicon Cor

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