Cadence Significantly Accelerates Chip Design With New Virtuoso Layout Suite for Electrically Aware Design

Cadence Significantly Accelerates Chip Design With New Virtuoso Layout Suite for Electrically Aware Design

SAN JOSE, CA — (Marketwired) — 07/10/13 — Cadence Design Systems (NASDAQ: CDNS)HIGHLIGHTS:Cadence Virtuoso Layout Suite Electrically Aware Design (EAD) can save engineers days to weeks of design time by enabling real-time parasitic extraction during layout.New product and methodology reduces need for multiple design iterations and "over design," translating to better performance and less area.Offering increased design team productivity and circuit performance for custom ICs, Cadenc

TSMC Expands Collaboration With Cadence on Virtuoso Custom Design Platform

TSMC Expands Collaboration With Cadence on Virtuoso Custom Design Platform

SAN JOSE, CA — (Marketwired) — 07/08/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)HIGHLIGHTS:TSMC to create and deliver native SKILL®-based PDKs in support of the Cadence® Virtuoso® platform to provide customers with the best user experience and highest level of accuracyWorld-s leading foundry deploys Virtuoso platform for custom design needs in advanced nodes, including 16-nanometer FinFET designsKey tools include Virtuoso Schematic Editor, Analog Design Environment, Virtuoso

Cadence Announces Second Quarter 2013 Financial Results Webcast

Cadence Announces Second Quarter 2013 Financial Results Webcast

SAN JOSE, CA — (Marketwired) — 07/05/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Cadence Design Systems, Inc. (NASDAQ: CDNS) to announce second quarter 2013 financial results via webcast.You are invited to attend the second quarter 2013 financial results audio webcast. Participating on the webcast will be Lip-Bu Tan, president and chief executive officer, and Geoff Ribar, senior vice president and chief financial officer.The webcast will begin Wednesday, July 24, 2013 at 2 p.m. (Pacific)

New Cadence Energy-Efficient PCI Express IP Helps Reduce Power Consumption for Datacenter and Enterprise Applications

New Cadence Energy-Efficient PCI Express IP Helps Reduce Power Consumption for Datacenter and Enterprise Applications

SAN JOSE, CA — (Marketwired) — 06/26/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)HIGHLIGHTSInnovative circuit calibration technique in new Cadence® PCI Express 3.0 solution enables customers to meet aggressive active power goals.Advanced power and clock management capabilities reduce standby current by 100XOptimized transition time latency between active and sleep statesAddressing the design challenge of reducing energy consumption of power-hungry datacenters and enterprise applicati

Media Alert: Cadence to Showcase Comprehensive PCI Express IP and Verification Solutions at PCI-SIG 2013

Media Alert: Cadence to Showcase Comprehensive PCI Express IP and Verification Solutions at PCI-SIG 2013

SAN JOSE, CA — (Marketwired) — 06/20/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced its participation at , an annual conference that provides comprehensive training on all aspects of the PCI (peripheral component interconnect) standard.Visitors to the Cadence booth (#9) can participate in the following demonstrations:Low-power PCIe controller and PHYMobile PCIe controller and MIPI M-PHYPCIe with TripleCheck IP ValidatorChip-

Cadence Completes Acquisition of Evatronix IP Business

Cadence Completes Acquisition of Evatronix IP Business

SAN JOSE, CA — (Marketwired) — 06/13/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has completed the acquisition of the IP business of Poland-based Evatronix, SA SKA. Further strengthening Cadence-s portfolio of intellectual property cores, Evatronix delivers a silicon-proven IP portfolio, which includes certified USB 2.0/3.0, MIPI, display, and storage controllers, which are highly complementary to Cadence-s IP pro

PMC Adopts Cadence Physical Verification System as Signoff Technology for Large Complex SoC

PMC Adopts Cadence Physical Verification System as Signoff Technology for Large Complex SoC

SAN JOSE, CA — (Marketwired) — 05/30/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)HIGHLIGHTSPMC is producing working silicon on 65- and 40-nanometer designs, and is currently deploying the product for its 28-nanometer designs.Technology chosen for turnaround time and ready foundry supportPhysical Verification System signoff decks certified by major foundriesCadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that PMC® has adopt

Cadence Design Tools Certified for TSMC 16nm FinFET Process and for TSMC 20nm Process

Cadence Design Tools Certified for TSMC 16nm FinFET Process and for TSMC 20nm Process

SAN JOSE, CA — (Marketwired) — 05/29/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)DRM and SPICE model V0.1 tool certification provides chip designers early access to TSMC 16-nanometer FinFET processFull flow certification achieved for TSMC 20-nanometer processCadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that several of its system-on-chip development tools have achieved version 0.1 of design rule manual (DRM) and SPICE model

Cadence Completes Acquisition of Cosmic Circuits

Cadence Completes Acquisition of Cosmic Circuits

SAN JOSE, CA — (Marketwired) — 05/23/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it has completed the acquisition of Cosmic Circuits Private Limited, a leading provider of analog and mixed signal intellectual property (IP) cores. Cosmic Circuits offers silicon-proven IP solutions in connectivity and advanced mixed-signal technologies in the 40nm and 28nm process nodes, with 20nm and FinFET development well underway.T

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