eda Archives - Page 3 of 13

Cadence Introduces New Family of Silicon-Proven High Performance Data Converter IP for Advanced 28nm Node

By Publisher on October 10, 2013 Networking, Picture Gallery

SAN JOSE, CA — (Marketwired) — 10/10/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Highlights:IP family delivers up to 10x faster conversion rate than available competing IP solutionsHigh-performance cores enable next-generation applications, such as WiGig (802.11ad)Broad IP family offering for consumer, mobile, infrastructure and industrial marketsCadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today introduced a suite of ultra-fast, low-power

Cadence Offers Industry-s First IP Core Solution Supporting DTS Neural Surround

By Publisher on October 10, 2013 Networking, Picture Gallery

Tensilica HiFi Audio/Voice DSP Brings Home Theater Experience to Cars and A/V Receivers

UPDATE: Cadence Introduces Spectre XPS, a New FastSPICE Simulator Delivering up to 10X Faster Throughput

By Publisher on October 9, 2013 Hardware, Picture Gallery

BANGALORE, INDIA — (Marketwired) — 10/09/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Highlights:Spectre XPS (eXtensive Partitioning Simulator), featuring a breakthrough partitioning technology, enables higher capacity and faster simulation while requiring two to three times less system memoryHigh-performance simulator delivers uniquely accurate timing analysis required for advanced-node, low-power mobile applicationsThe new FastSPICE technology unites with the existing Spectre environmen

Cadence Introduces Spectre XPS, a New FastSPICE Simulator Delivering up to 10X Faster Throughput

By Publisher on October 9, 2013 Hardware, Picture Gallery

BANGALORE, INDIA — (Marketwired) — 10/09/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Highlights:Spectre XPS (eXtensive Partitioning Simulator), featuring a breakthrough partitioning technology, enables higher capacity and faster simulation while requiring two to three times less system memoryHigh-performance simulator delivers uniquely accurate timing analysis required for advanced-node, low-power mobile applicationsThe new FastSPICE technology unites with the existing Spectre environmen

Cadence Announces Third Quarter 2013 Financial Results Webcast

By Publisher on October 4, 2013 Networking, Picture Gallery

SAN JOSE, CA — (Marketwired) — 10/04/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Cadence Design Systems, Inc. (NASDAQ: CDNS) to announce third quarter 2013 financial results via webcast.You are invited to attend the third quarter 2013 financial results audio webcast. Participating on the webcast will be Lip-Bu Tan, president and chief executive officer, and Geoff Ribar, senior vice president and chief financial officer.The webcast will begin Wednesday, Oct. 23, 2013 at 2 p.m. (Pacific)/5

Media Alert: Cadence Hosts Mixed-Signal Technology Summit

By Publisher on October 3, 2013 Hardware, Picture Gallery

SAN JOSE, CA — (Marketwired) — 10/03/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced it is hosting a Mixed-Signal Technology Summit, October 10 at its San Jose headquarters.Attendees of this free day-long event will have the opportunity to learn from experts at Cadence and other leading companies about the latest mixed signal design methodologies, and new Cadence technologies such as support for System Verilog real number mod

Cadence Receives Three TSMC Partner of the Year Awards for Design IP, 16nm FinFET and 3D-IC Solutions

By Publisher on October 1, 2013 Networking, Picture Gallery

SAN JOSE, CA — (Marketwired) — 10/01/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today received three TSMC Partner of the Year Awards during TSMC-s Open Innovation Platform forum — accepting the most awards from the event. Cadence was presented awards for three different categories including awards for analog/mixed signal IP, 16nm FinFET design infrastructure, and 3D-IC design solutions. The awards underscore the deep collaboration betw

Cadence Digital and Custom/Analog Tools Included in TSMC Reference Flows to Enable 16nm FinFET Designs

By Publisher on September 19, 2013 Networking, Picture Gallery

SAN JOSE, CA — (Marketwired) — 09/19/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)HIGHLIGHTSDigital design tools support TSMC 16nm Reference Flow using a 16nm FinFET quad-core design with an ARM Cortex-A15, pairing the most advanced geometry with the high-performance ARM Cortex mobile processorCustom/analog design tools support TSMC 16nm Custom Design Reference Flow with optimized 16nm native SKILL PDKs, granting designers immediate access to the most advanced Virtuoso featuresCadence too

TSMC and Cadence Deliver 3D-IC Reference Flow for True 3D Stacking

By Publisher on September 19, 2013 Picture Gallery, Software

SAN JOSE, CA — (Marketwired) — 09/19/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Highlights:New reference flow enhances CoWoS (chip-on-wafer-on-substrate) chip designFlow certified using a memory-on-logic design with a 3D stackCadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that TSMC has collaborated with Cadence to develop a 3D-IC reference flow which features innovative true 3D stacking. The flow, validated on a memory-on-lo

Media Alert: Cadence to Showcase New Allegro Sigrity Power Integrity Product at PCB West

By Publisher on September 18, 2013 Networking, Picture Gallery

SAN JOSE, CA — (Marketwired) — 09/18/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, will showcase Allegro® Sigrity Power Integrity, a new product that integrates Cadence® Allegro and Sigrity technology, on Sept. 25 at booth #406 at the conference.Allegro Sigrity Power Integrity enhances efficiencies for faster time to market. The new tool enables design teams to be proactively involved in power integrity decisions, while granting e