CAMBRIDGE, United Kingdom, 1 June 2017: UltraSoC, the leading developer of on-chip monitoring and analytics IP, today announced that Alberto Sangiovanni-Vincentelli, a founding-father and driving force in both commercial and technological developments in the electronics design industry, has joined the company’s Strategic Advisory Board.
Sangiovanni-Vincentelli brings significant experience of direct relevance to UltraSoC given its target customers and vertical market applications. In the commer
SAN JOSE, CA — (Marketwired) — 12/10/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Digital Voice Systems, Inc. (DVSI) AMBE® Advanced Multi-Band Excitation wideband decoder software has been ported to the Cadence® Tensilica® HiFi Audio/Voice DSP family to enhance high-quality voice compression at low bit rates."The Cadence Tensilica HiFi Audio/Voice DSP family is an ideal, efficient platform for our AMB
SAN JOSE, CA — (Marketwired) — 11/25/13 — In the news release, "Cadence Receives Two TSMC Customers- Choice Awards," issued earlier today by Cadence Design Systems, Inc. (NASDAQ: CDNS), we are advised by the company that the customer quote in the third paragraph has changed. Complete corrected text follows.SAN JOSE, CA — Nov 25, 2013 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that the company has received two Cu
SAN JOSE, CA — (Marketwired) — 11/25/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Learn how to achieve faster design closure with physically-aware design knowledge at this year-s Front-End Design (FED) Summit. This day-long event will educate attendees on how to save design closure time and boost performance by incorporating knowledge of physically-aware design early into the front-end design implementation flow.Thursday, December 5, 2013Cadence Design Systems
Building 10 Auditorium
2655
SAN JOSE, CA — (Marketwired) — 11/25/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that the company has received two Customers- Choice Awards for papers delivered at TSMC-s recent Open Innovation Platform (OIP) Ecosystem Forum. The papers were entitled, "Resistance, Pin Access and FinFET Parasitics," authored by Paul Cunningham, Rachid Salik, Hitendra Divecha and Rahul Deokar; and "16G Multi-Standard SerDes I
SAN JOSE, CA — (Marketwired) — 11/20/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Highlights:New capabilities in RTL Compiler bring physical considerations earlier in the synthesis process for better quality of resultsDelivers up to 15 percent improvement in power, performance and area in new version of RTL CompilerCadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design automation, today introduced the Encounter® RTL Compiler version 13.1, which includes a ne
SAN JOSE, CA — (Marketwired) — 11/18/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design automation, today announced that Faraday Technology Corp., based in Hsinchu, Taiwan, deployed a full Cadence® tool flow to create its largest System-on-Chip (SoC), a 300-million-gate design for a 4G base station. By using Cadence Encounter® digital design tools in Faraday-s hierarchical flow, the design team completed this complex SoC, from data-in to tapeout, i
SAN JOSE, CA — (Marketwired) — 11/13/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS) — If you want to get on the fast track to design signoff, don-t miss Cadence-s Signoff Summit — a day-long event that will help you shave weeks off design closure.Thursday, November 21, 2013Cadence Design Systems
Building 10 Auditorium
2655 Seely Ave,
San Jose, CA 95134The summit will include keynote addresses plus sessions covering the multiple solution components that comprise a comprehensive signoff s
SAN JOSE, CA — (Marketwired) — 11/12/13 — Cadence Design Systems, Inc. (NASDAQ: CDNS)Highlights:New power integrity analysis engine with massively parallel execution brings up to 10X faster performanceNew hierarchical architecture supports very large designs up to 1 billion instancesTightly integrated with key Cadence tools throughout the design flow, including Cadence Tempus Timing Signoff Solution, for the fastest design closure in the industryAddressing the critical power challenges faced
