SAN JOSE, CA — (Marketwired) — 09/10/15 — eSilicon Corporation, Northwest Logic and SK Hynix today announced they have created a fully working HBM hardware demonstration. This demonstration uses an advanced FPGA containing Northwest Logic–s HBM Controller Core and FPGA-based HBM PHY and SK Hynix HBM devices. eSilicon packaged the FPGA and HBM devices on an organic interposer. This demonstration is further indication that HBM is ready to be used by the market to implement a wide variety of h
SAN JOSE, CA — (Marketwired) — 07/09/15 — eSilicon Corporation, a leading independent semiconductor design and manufacturing solutions provider, today announced the addition of Jens Andersen as its new vice president of business development for the recently announced eSilicon® STAR online IC design virtualization platform."With nearly 20 years– experience in business and EDA technology, Jens will play a pivotal role in driving existing and new programs supporting our leadership pos
SAN JOSE, CA — (Marketwired) — 07/08/15 — eSilicon Corporation, a leading independent semiconductor design and manufacturing solutions provider, today announced the promotion of Colby Gartin to vice president and general counsel. Gartin is responsible for eSilicon–s commercial agreements, strategic transactions, IP portfolio, litigation and corporate governance matters. Colby reports to Jack Harding, CEO and president."Colby–s extensive legal and senior management expertise in advisin
SAN JOSE, CA — (Marketwired) — 04/29/15 –Javier DeLaCruz, eSilicon–s senior director of product strategyHoliday Inn Conference Center
242 Adams
Boxborough, Massachusetts 01719May 5, 2015
10:40 AMVarious market dynamics are influencing the adoption of 2.5D integration. Recent developments have enabled 2.5D to provide feature enhancements, but if applied well may also provide significant cost benefits over what can be otherwise executed.As a senior director of product strategy at eSilicon Cor
SAN JOSE, CA — (Marketwired) — 04/20/15 –Monterey Beach Resort
2600 Sand Dunes Drive
Monterey, California 93940April 23-24, 2015
Day two: Low Power DesignPrasad Subramaniam, eSilicon
vice president of R&D and design technologyLow-Power Design MethodologiesLow Power Panel: Low Power Tools, Techniques & and Verification: Brian Fuller, CadenceBernard Murphy, AtrentaSteve Carlson, CadencePrasad Subramaniam, eSiliconPat Sheridan, SynopsysTom Quan, TSMCThe Electronic Design Process Symposi
SAN JOSE, CA — (Marketwired) — 04/16/15 –DoubleTree by Hilton Hotel San Jose
2050 Gateway Place
San Jose, California 95110April 21, 2015Daniel Nenni, SemiWiki.com CEO & FounderJack Harding, eSilicon, president & CEOWally Rhines, Mentor Graphics, CEO & COBGiorgio Cesana, STMicroelectronics, director of technologyLluis Paris, TSMC, deputy director of worldwide IP allianceThe system on chip (SoC) business seriously challenged the semiconductor foundries at 28nm with increased integr
