OTTAWA and SANTA CLARA, CA — (Marketwire) — 10/11/11 —
Sidense exhibiting and speaking at the TSMC OIP Forum
San Jose Convention Center
150 West San Carlos Street
San Jose, CA 95110
Tuesday, October 18
8:00AM to 5:00PM
Sidense to present at 2:00PM:
Sidense Corp. provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company-s innovative one-transistor 1T-Fuse architecture provides the industry-s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (LNVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense SiPROM, SLP and ULP memory products, embedded in over 160 customer designs, are available from 180nm down to 40nm and are scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic. For more information, please visit .
An invitation-only event, the OIP Forum features a one-day conference including keynote from Dr. Shang-yi Chiang, TSMC Senior VP of R&D, four invited talks by CEOs and General Managers from ARM, Cadence, Mentor and Synopsys, 24 selected technical papers from TSMC EDA, IP, Design Center Alliance and Value Chain Aggregator partners, and an Ecosystem Pavilion featuring up to 80 partner companies.
For more information or to schedule a meeting with Sidense, please contact:
Jim Lipman
Sidense
925-606-1370
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