OTTAWA, ON and SANTA CLARA, CA — (Marketwired) — 09/23/14 —
Sidense exhibiting at the TSMC OIP Forum
San Jose Convention Center
150 West San Carlos Street
San Jose, CA 95110
Booth #201
Tuesday, September 30
8:00AM to 5:30PM
In their booth, Sidense will show a slide presentation entitled, discussing how the Company ensures reliability for its OTP IP Macros and reviewing the OTP products Sidense has already qualified to meet TSMC9000 assessment criteria, as well as other OTP products in the TSMC9000 pipeline. Specifically for mobile applications, we will discuss how to obtain high-security OTP at both the bit-cell level and in supporting circuitry.
The presentation will include information on several families of 1T-OTP-based memory subsystems under development that specifically address mobile devices. Sidense will also discuss a 1T-OTP split-channel NVM structure for TSMC–s 16nm FinFET process and how our 16nm OTP design concepts are transferable to 10nm.
Sidense Corp. provides very dense, highly reliable and secure non-volatile one-time programmable (OTP) Logic Non-Volatile Memory (LNVM) IP for use in standard-logic CMOS processes. The Company, with over 120 patents granted or pending, licenses OTP memory IP based on its innovative one-transistor 1T-Fuse bit cell, which does not require extra masks or process steps to manufacture. Sidense 1T-OTP macros provide a better field-programmable, reliable and cost-effective solution than flash, mask ROM, eFuse and other embedded and off-chip NVM technologies for many code storage, encryption key, analog trimming and device configuration uses.
125 companies, including many of the top fabless semiconductor manufacturers and IDMs, have adopted Sidense 1T-OTP as their NVM solution in more than 400 designs. Customers are realizing outstanding savings in solution cost and power consumption along with better security and reliability for applications ranging from mobile and consumer devices to high-temperature, high-reliability automotive and industrial electronics. The IP is offered at and supported by all top-tier semiconductor foundries and selected IDMs. Sidense is headquartered in Ottawa, Canada with sales offices worldwide. For more information, please visit .
The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings together TSMC–s design ecosystem companies and customers to share real case solutions to today–s design challenges. Success stories that illustrate best practice in TSMC–s design ecosystem will highlight the event.
At this year–s event you will hear directly from TSMC OIP companies about how to leverage their technology to your design challenges! This year, the forum is a day-long conference kicking-off with trend-setting addresses and announcements from TSMC executives. The technical sessions feature presentations from TSMC–s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies and an Ecosystem Pavilion featuring up to 80 member companies showcasing their products and services. For more information, go to:
For more information or to schedule a meeting with Sidense, please contact:
Jim Lipman
Sidense
925-606-1370
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