Tweet

Verific Design Automation–s Parser Platform Integrated With Tortuga Logic–s Hardware Security Design and Analysis Toolkit

ALAMEDA, CA — (Marketwired) — 10/20/15 — , transforming the way hardware designers and system architects test the security of hardware design, has licensed the Parser Platform from , the recognized leader of SystemVerilog, VHDL and UPF parsers used throughout the semiconductor industry.

Verific–s SystemVerilog and VHDL parsers have been implemented as the front end to Prospect, Tortuga Logic–s Hardware Security Design and Analysis Toolkit that uncovers hidden bugs and proves the absence of vulnerabilities in hardware designs.

“Verific–s Parser Platform is an important component of our hardware security software,” confirms Dr. Jason Oberg, co-founder and chief executive officer (CEO) of Tortuga Logic. “We were able to save countless hours by partnering with Verific. We used its thoroughly tested parsers and were able to focus on developing software that identifies security vulnerabilities in hardware designs.”

Leveraging Verific–s Parser Platform, Prospect reads a register transfer level (RTL) description of the design and performs a thorough analysis to uncover a broad range of vulnerabilities. It does so by automatically generating SystemVerilog assertions and instrumentation from a high-level description of the security properties.

“Security is becoming an increasing concern and we applaud Tortuga Logic–s security experts for tackling this problem,” says Michiel Ligthart, Verific–s president and chief operating officer. “The founders– decision to choose our parser platform enabled the early release of this significant new toolset and keep system designs secure.”

Verific–s Parser Platforms are in production and development use today at companies worldwide, from cybersecurity startups such as Tortuga Logic to established Fortune 500 semiconductor vendors. Applications vary from analysis, simulation, formal verification and synthesis to emulation and virtual prototyping, in-circuit debug and design-for-test. Parser Platforms are distributed as C++ source code and compile on all 32- and 64-bit Unix, Linux and Windows operating systems. Its Parser Platforms include support for SystemVerilog, Verilog, VHDL and UPF, and provide C++, Python and Perl APIs.

, part of the emerging Design-for-Security market, has the goal to solve security-specific problems, minimizing security breaches in hardware and systems by automating the process of verifying their security properties. It has developed a comprehensive Hardware Security Design and Analysis Toolkit, transforming the way hardware designers and system architects test the security of hardware designs. More information can be found at: Email:

, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific–s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: Website:

Verific Design Automation and Tortuga Logic acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822